The present invention generally relates to software development and more particularly to a technique for reducing constant loading overhead in a RISC processor.
Unlike CISC processors which may process instructions of variable lengths, RISC processors may require a fixed instruction size. As a result, a plurality of instructions may be necessary to load a long constant on a register in RISC processors. For example, in an IBM POWER™ processor, loading of a 32-bit constant 0x12345678 may be achieved by combining two instructions in the following fashion: (1) lis reg, 0x1234 and (2) on reg, reg, 0x5678.
Based on an instruction Us in item (1), a value shifting a constant 0x1234 by 16 bits to the left may be stored in a register reg. In this way, the digits of the upper half of the 32-bit constant 0x12345678 are set as upper 16 bits of the register reg. Next, based on an instruction on in item (2), a logical sum of the register reg and a constant 0x5678 may be written in the register reg. In doing so, the digits of the lower half of the 32-bit constant 0x12345678 may be set as lower 16 bits of the register reg. As a result, the 32-bit constant 0x12345678 may be loaded on the register reg.
As the number of instructions increases, execution time, cost, and pressure on an instruction cache may also increase. For example, loading of a 64-bit constant may require creating a memory region (also referred to as Table of Contents: TOC) with aligned constants during compilation. Then, one register (hereinafter “TOC register”) may be allocated to hold a pointer indicating the TOC. To use a constant, the TOC register may load the constant from the memory. This may reduce the number of instructions for loading the constant but may substantially increase pressure on the data cache.